Index: src/UnwindRegistersRestore.S =================================================================== --- src/UnwindRegistersRestore.S (revision 311547) +++ src/UnwindRegistersRestore.S (working copy) @@ -96,20 +96,20 @@ #elif defined(__ppc__) DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind13Registers_ppc6jumptoEv) -; -; void libunwind::Registers_ppc::jumpto() -; -; On entry: -; thread_state pointer is in r3 -; +// +// void libunwind::Registers_ppc::jumpto() +// +// On entry: +// thread_state pointer is in r3 +// - ; restore integral registerrs - ; skip r0 for now - ; skip r1 for now + // restore integral registerrs + // skip r0 for now + // skip r1 for now lwz r2, 16(r3) - ; skip r3 for now - ; skip r4 for now - ; skip r5 for now + // skip r3 for now + // skip r4 for now + // skip r5 for now lwz r6, 32(r3) lwz r7, 36(r3) lwz r8, 40(r3) @@ -137,7 +137,7 @@ lwz r30,128(r3) lwz r31,132(r3) - ; restore float registers + // restore float registers lfd f0, 160(r3) lfd f1, 168(r3) lfd f2, 176(r3) @@ -171,46 +171,45 @@ lfd f30,400(r3) lfd f31,408(r3) - ; restore vector registers if any are in use - lwz r5,156(r3) ; test VRsave + // restore vector registers if any are in use + lwz r5,156(r3) // test VRsave cmpwi r5,0 beq Lnovec subi r4,r1,16 - rlwinm r4,r4,0,0,27 ; mask low 4-bits - ; r4 is now a 16-byte aligned pointer into the red zone - ; the _vectorRegisters may not be 16-byte aligned so copy via red zone temp buffer + rlwinm r4,r4,0,0,27 // mask low 4-bits + // r4 is now a 16-byte aligned pointer into the red zone + // the _vectorRegisters may not be 16-byte aligned so copy via red zone temp buffer +#define LOAD_VECTOR_UNALIGNEDl(_index) \ + andis. r0,r5,(1<<(15-_index)) SEPARATOR \ + beq Ldone ## _index SEPARATOR \ + lwz r0, 424+_index*16(r3) SEPARATOR \ + stw r0, 0(r4) SEPARATOR \ + lwz r0, 424+_index*16+4(r3) SEPARATOR \ + stw r0, 4(r4) SEPARATOR \ + lwz r0, 424+_index*16+8(r3) SEPARATOR \ + stw r0, 8(r4) SEPARATOR \ + lwz r0, 424+_index*16+12(r3) SEPARATOR \ + stw r0, 12(r4) SEPARATOR \ + lvx v ## _index,0,r4 SEPARATOR \ +Ldone ## _index: -#define LOAD_VECTOR_UNALIGNEDl(_index) \ - andis. r0,r5,(1<<(15-_index)) @\ - beq Ldone ## _index @\ - lwz r0, 424+_index*16(r3) @\ - stw r0, 0(r4) @\ - lwz r0, 424+_index*16+4(r3) @\ - stw r0, 4(r4) @\ - lwz r0, 424+_index*16+8(r3) @\ - stw r0, 8(r4) @\ - lwz r0, 424+_index*16+12(r3)@\ - stw r0, 12(r4) @\ - lvx v ## _index,0,r4 @\ +#define LOAD_VECTOR_UNALIGNEDh(_index) \ + andi. r0,r5,(1<<(31-_index)) SEPARATOR \ + beq Ldone ## _index SEPARATOR \ + lwz r0, 424+_index*16(r3) SEPARATOR \ + stw r0, 0(r4) SEPARATOR \ + lwz r0, 424+_index*16+4(r3) SEPARATOR \ + stw r0, 4(r4) SEPARATOR \ + lwz r0, 424+_index*16+8(r3) SEPARATOR \ + stw r0, 8(r4) SEPARATOR \ + lwz r0, 424+_index*16+12(r3) SEPARATOR \ + stw r0, 12(r4) SEPARATOR \ + lvx v ## _index,0,r4 SEPARATOR \ Ldone ## _index: -#define LOAD_VECTOR_UNALIGNEDh(_index) \ - andi. r0,r5,(1<<(31-_index)) @\ - beq Ldone ## _index @\ - lwz r0, 424+_index*16(r3) @\ - stw r0, 0(r4) @\ - lwz r0, 424+_index*16+4(r3) @\ - stw r0, 4(r4) @\ - lwz r0, 424+_index*16+8(r3) @\ - stw r0, 8(r4) @\ - lwz r0, 424+_index*16+12(r3)@\ - stw r0, 12(r4) @\ - lvx v ## _index,0,r4 @\ - Ldone ## _index: - LOAD_VECTOR_UNALIGNEDl(0) LOAD_VECTOR_UNALIGNEDl(1) LOAD_VECTOR_UNALIGNEDl(2) @@ -245,17 +244,17 @@ LOAD_VECTOR_UNALIGNEDh(31) Lnovec: - lwz r0, 136(r3) ; __cr - mtocrf 255,r0 - lwz r0, 148(r3) ; __ctr + lwz r0, 136(r3) // __cr + mtcrf 255,r0 + lwz r0, 148(r3) // __ctr mtctr r0 - lwz r0, 0(r3) ; __ssr0 + lwz r0, 0(r3) // __ssr0 mtctr r0 - lwz r0, 8(r3) ; do r0 now - lwz r5,28(r3) ; do r5 now - lwz r4,24(r3) ; do r4 now - lwz r1,12(r3) ; do sp now - lwz r3,20(r3) ; do r3 last + lwz r0, 8(r3) // do r0 now + lwz r5,28(r3) // do r5 now + lwz r4,24(r3) // do r4 now + lwz r1,12(r3) // do sp now + lwz r3,20(r3) // do r3 last bctr #elif defined(__arm64__) || defined(__aarch64__) @@ -365,6 +364,10 @@ @ these registers implies they are, actually, available on the target, so @ it's ok to execute. @ So, generate the instruction using the corresponding coprocessor mnemonic. +// RICH: Check this. +// RICH#if __ARM_ARCH < 7 || !defined(__VFP_FP__) +// RICH ldc p11, cr0, [r0], {0x20} @ fldmiad r0, {d0-d15} +// RICH#else vldmia r0, {d0-d15} JMP(lr) @@ -435,9 +438,20 @@ ldc2 p1, cr10, [r0], #4 @ wldrw wCGR2, [r0], #4 ldc2 p1, cr11, [r0], #4 @ wldrw wCGR3, [r0], #4 JMP(lr) - #endif +#elif __microblaze__ + // __ELLCC__ +DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind16Registers_microblaze6jumptoEv) + rtsd r15, 8 + ori r3, r0,0 // Branch delay slot. + +#elif __mips__ + // __ELLCC__ +DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind16Registers_mips6jumptoEv) + jr $ra + li $2, 0 // Branch delay slot. + #elif defined(__or1k__) DEFINE_LIBUNWIND_PRIVATE_FUNCTION(_ZN9libunwind14Registers_or1k6jumptoEv) Index: src/UnwindRegistersSave.S =================================================================== --- src/UnwindRegistersSave.S (revision 311547) +++ src/UnwindRegistersSave.S (working copy) @@ -94,20 +94,21 @@ # # Just trap for the time being. DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + .set mips32r2 teq $0, $0 #elif defined(__ppc__) -; -; extern int unw_getcontext(unw_context_t* thread_state) -; -; On entry: -; thread_state pointer is in r3 -; +// +// extern int unw_getcontext(unw_context_t* thread_state) +// +// On entry: +// thread_state pointer is in r3 +// DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) stw r0, 8(r3) mflr r0 - stw r0, 0(r3) ; store lr as ssr0 + stw r0, 0(r3) // store lr as ssr0 stw r1, 12(r3) stw r2, 16(r3) stw r3, 20(r3) @@ -140,17 +141,17 @@ stw r30,128(r3) stw r31,132(r3) - ; save VRSave register + // save VRSave register mfspr r0,256 stw r0,156(r3) - ; save CR registers + // save CR registers mfcr r0 stw r0,136(r3) - ; save CTR register + // save CTR register mfctr r0 stw r0,148(r3) - ; save float registers + // save float registers stfd f0, 160(r3) stfd f1, 168(r3) stfd f2, 176(r3) @@ -185,21 +186,21 @@ stfd f31,408(r3) - ; save vector registers + // save vector registers subi r4,r1,16 - rlwinm r4,r4,0,0,27 ; mask low 4-bits - ; r4 is now a 16-byte aligned pointer into the red zone + rlwinm r4,r4,0,0,27 // mask low 4-bits + // r4 is now a 16-byte aligned pointer into the red zone #define SAVE_VECTOR_UNALIGNED(_vec, _offset) \ - stvx _vec,0,r4 @\ - lwz r5, 0(r4) @\ - stw r5, _offset(r3) @\ - lwz r5, 4(r4) @\ - stw r5, _offset+4(r3) @\ - lwz r5, 8(r4) @\ - stw r5, _offset+8(r3) @\ - lwz r5, 12(r4) @\ + stvx _vec,0,r4 SEPARATOR \ + lwz r5, 0(r4) SEPARATOR \ + stw r5, _offset(r3) SEPARATOR \ + lwz r5, 4(r4) SEPARATOR \ + stw r5, _offset+4(r3) SEPARATOR \ + lwz r5, 8(r4) SEPARATOR \ + stw r5, _offset+8(r3) SEPARATOR \ + lwz r5, 12(r4) SEPARATOR \ stw r5, _offset+12(r3) SAVE_VECTOR_UNALIGNED( v0, 424+0x000) @@ -235,7 +236,7 @@ SAVE_VECTOR_UNALIGNED(v30, 424+0x1E0) SAVE_VECTOR_UNALIGNED(v31, 424+0x1F0) - li r3, 0 ; return UNW_ESUCCESS + li r3, 0 // return UNW_ESUCCESS blr @@ -289,6 +290,19 @@ mov x0, #0 // return UNW_ESUCCESS ret +#elif __microblaze__ + + // __ELLCC__ +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + rtsd r15, 8 + ori r3, r0,0 // Branch delay slot. + +#elif __mips__ + // __ELLCC__ +DEFINE_LIBUNWIND_FUNCTION(unw_getcontext) + jr $ra + li $2, 0 // Branch delay slot. + #elif defined(__arm__) && !defined(__APPLE__) #if !defined(__ARM_ARCH_ISA_ARM) Index: src/assembly.h =================================================================== --- src/assembly.h (revision 311547) +++ src/assembly.h (working copy) @@ -16,7 +16,8 @@ #ifndef UNWIND_ASSEMBLY_H #define UNWIND_ASSEMBLY_H -#if defined(__POWERPC__) || defined(__powerpc__) || defined(__ppc__) +#if (defined(__POWERPC__) || defined(__powerpc__) || defined(__ppc__)) && \ + !defined(__linux__) #define SEPARATOR @ #elif defined(__arm64__) #define SEPARATOR %% @@ -24,6 +25,106 @@ #define SEPARATOR ; #endif +#if (defined(__POWERPC__) || defined(__powerpc__) || defined(__ppc__)) && \ + defined(__linux__) + #define r0 0 + #define r1 1 + #define r2 2 + #define r3 3 + #define r4 4 + #define r5 5 + #define r6 6 + #define r7 7 + #define r8 8 + #define r9 9 + #define r10 10 + #define r11 11 + #define r12 12 + #define r13 13 + #define r14 14 + #define r15 15 + #define r16 16 + #define r17 17 + #define r18 18 + #define r19 19 + #define r20 20 + #define r21 21 + #define r22 22 + #define r23 23 + #define r24 24 + #define r25 25 + #define r26 26 + #define r27 27 + #define r28 28 + #define r29 29 + #define r30 30 + #define r31 31 + #define f0 0 + #define f1 1 + #define f2 2 + #define f3 3 + #define f4 4 + #define f5 5 + #define f6 6 + #define f7 7 + #define f8 8 + #define f9 9 + #define f10 10 + #define f11 11 + #define f12 12 + #define f13 13 + #define f14 14 + #define f15 15 + #define f16 16 + #define f17 17 + #define f18 18 + #define f19 19 + #define f20 20 + #define f21 21 + #define f22 22 + #define f23 23 + #define f24 24 + #define f25 25 + #define f26 26 + #define f27 27 + #define f28 28 + #define f29 29 + #define f30 30 + #define f31 31 + #define v0 0 + #define v1 1 + #define v2 2 + #define v3 3 + #define v4 4 + #define v5 5 + #define v6 6 + #define v7 7 + #define v8 8 + #define v9 9 + #define v10 10 + #define v11 11 + #define v12 12 + #define v13 13 + #define v14 14 + #define v15 15 + #define v16 16 + #define v17 17 + #define v18 18 + #define v19 19 + #define v20 20 + #define v21 21 + #define v22 22 + #define v23 23 + #define v24 24 + #define v25 25 + #define v26 26 + #define v27 27 + #define v28 28 + #define v29 29 + #define v30 30 + #define v31 31 +#endif + #if defined(__APPLE__) #define HIDDEN_DIRECTIVE .private_extern #else Index: src/libunwind.cpp =================================================================== --- src/libunwind.cpp (revision 311547) +++ src/libunwind.cpp (working copy) @@ -59,14 +59,20 @@ #elif defined(__or1k__) # define REGISTER_KIND Registers_or1k #elif defined(__mips__) -# warning The MIPS architecture is not supported. +// RICH: TODO +#elif defined(__microblaze__) +// RICH: TODO #else # error Architecture not supported #endif + +#ifdef REGISTER_KIND // Use "placement new" to allocate UnwindCursor in the cursor buffer. new ((void *)cursor) UnwindCursor( context, LocalAddressSpace::sThisAddressSpace); #undef REGISTER_KIND +#endif + AbstractUnwindCursor *co = (AbstractUnwindCursor *)cursor; co->setInfoBasedOnIPRegister();