Support for Cortex-M0+

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This topic contains 1 reply, has 1 voice, and was last updated by  Emmanuel Blot 7 years, 4 months ago.

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    Emmanuel Blot


    Is it possible to use ecc to cross-compile for Cortex-M0+ targets?
    I’ve been looking to the blog pages, and I’m not sure if it is easily achievable.

    The only “officially” supported Cortex-M series is the Cortex-M3, which use a different ARM architecture.

    I have some additional questions:
    – what does mean the “engeabi” target suffix – i.e. how it differs from the ARM EABI. It seems it is based on linux that is. gnueabi, not EABI. Is this correct?
    – there is no libecc/lib/arm32v6-linux directory, although there is a libecc/config/arm32v6-linux that seems to refer to it
    – V6 seems to indicate a … ARMv6 architecture, but the ELF tools report ARMv7 kind of binaries:

    $ ecc-readelf -A libecc/lib/arm32v6sf-linux/crt1.o
    Attribute Section: aeabi
    File Attributes
      Tag_conformance: "2.09"
      Tag_CPU_name: "Cortex-A8"
      Tag_CPU_arch: v7
      Tag_CPU_arch_profile: Application
      Tag_ARM_ISA_use: Yes
      Tag_THUMB_ISA_use: Thumb-2
      Tag_FP_arch: VFPv3
      Tag_Advanced_SIMD_arch: NEONv1
      Tag_ABI_PCS_GOT_use: direct
      Tag_ABI_PCS_wchar_t: 4
      Tag_ABI_FP_denormal: Needed
      Tag_ABI_FP_exceptions: Needed
      Tag_ABI_FP_number_model: IEEE 754
      Tag_ABI_align_needed: 8-byte
      Tag_ABI_align_preserved: 8-byte, except leaf SP
      Tag_ABI_enum_size: int
      Tag_CPU_unaligned_access: v6
      Tag_ABI_FP_16bit_format: IEEE 754
      Tag_Virtualization_use: TrustZone

    … any help would be useful

    BTW, google found but I’m not able to find a link to this page. Is it up-to-date?

    Thanks a lot,


    Emmanuel Blot

    * is in the SVN repository, me bad
    * it seems an armv6m target should be defined to support Cortex-M0/M0+/M1
    * major issue: Musl does not support Cortex-M* CPUs for now (planned for musl 1.1.17) but worst: it does not seem that Thumb1 support is planned at all, and several musl low-level pieces are written with 32bit ARM / Thumb2 ISA. This seems to be a real show-stopper 🙁

    However, I would not need the a libc for a pure bare metal implementation. Only clang/llvm/compiler-rt are actually required.

    Therefore my initial question should be rewritten as: is it possible to use ELLCC to build bare-metal projects without libecc for Cortex-M0/M0+/M1? It would be nice to keep using the ELLCC infrastructure even in this limited mode.

    I guess the alternative is to build clang/llvm/compiler-rt from the sources, but that makes just-another-compiler installation and I do like ELLCC 🙂

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